This invention relates to wideband code division multiple access (WCDMA) for a communication system and more particularly to cell search for WCDMA using primary, secondary and tertiary synchronization codes.
Present code division multiple access (CDMA) systems are characterized by simultaneous transmission of different data signals over a common channel by assigning each signal a unique code. This unique code is matched with a code of a selected receiver to determine the proper recipient of a data signal. These different data signals arrive at the receiver via multiple paths due to ground clutter and unpredictable signal reflection. Additive effects of these multiple data signals at the receiver may result in significant fading or variation in received signal strength. In general, this fading due to multiple data paths may be diminished by spreading the transmitted energy over a wide bandwidth. This wide bandwidth results in greatly reduced fading compared to narrow band transmission modes such as frequency division multiple access (FDMA) or time division multiple access (TDMA).
New standards are continually emerging for net generation wideband code division multiple access (WCDMA) communication systems as described in U.S. Pat. No. 6,345,069, entitled Simplified Cell Search Scheme for First and Second Stage, issued Feb. 5, 2002, and incorporated herein by reference. These WCDMA systems are coherent communications systems with pilot symbol assisted channel estimation schemes. These pilot symbols are transmitted as quadrature phase shift keyed (QPSK) sown data in predetermined time frames to any receivers within the cell or within range The frames may propagate in a discontinuous transmission (DTX) mode within the cell. For voice traffic, transmission of user data occurs when the user speaks, but no data symbol transmission occurs when the user is silent. Similarly for packet data, the use data may be transmitted only when packets are ready to be sent. The frames include pilot symbols as well as other control symbols such as transmit power control (IPC) symbols and rate information (RI) symbols. These control symbols include multiple bits otherwise known as chips to distinguish them from data bits. The chip transmission time (TC), therefore, is equal to the symbol time rate (T) divided by the number of chips in the symbol (N) This number of chips in the symbol is the spreading factor.
A WCDMA base station must broadcast primary or first (FSC) and secondary (SSC) synchronization codes to properly establish communications with a mobile receiver. The FSC identifies the slot timing from the transmitting base station. The SSC further identifies a group of sixteen scrambling codes, one of which is assigned to the transmitting base station. Referring now to FIG. 1, there is a simplified block diagram of a circuit of the prior art for generating primary and secondary synchronization codes. These synchronization codes modulate or spread the transmitted signal so that a mobile receiver may identify it. Circuits 102 and 110 each produce a 256 cycle Hadamard sequence at leads 103 and 111, respectively. Either a true or a complement of a 16-cycle pseudorandom noise (PN) sequence, however, selectively modulates both sequences. This 16-cycle PN sequence is preferably a binary Lindner sequence given by Z={1,1,xe2x88x921,xe2x88x921,xe2x88x921,xe2x88x921,1,xe2x88x921,1, 1,xe2x88x921,1,1,1,xe2x88x921,1}. Each element of the Lindner sequence is further designated Z1-Z16, respectively. Circuit 108 generates a 256-cycle code at lead 109 as a product of the Lindner sequence and each element of the sequence. The resulting PN sequence at lead 109, therefore, has the form {Z,Z,xe2x88x92Z,xe2x88x92Z,xe2x88x92Z,xe2x88x92Z,Z,xe2x88x92Z,Z,Z,xe2x88x92Z,Z,Z,Z,xe2x88x92Z,Z}. Exclusive-OR circuit 112 modulates the Hadamard sequence on lead 111 with the PN sequence on lead 109, thereby producing a FSC on lead 114. Likewise, exclusive-OR circuit 104 modulates the Hadamard sequence on lead 103 with the PN sequence on lead 109, thereby producing an SSC on lead 106.
A WCDMA mobile communication system must initially acquire a signal from a remote base station to establish communications within a cell. This initial acquisition, however, is complicated by the presence of multiple unrelated signals from the base station that are intended for other mobile systems within the cell as well as signals from other base stations. The base station continually transmits a special signal at 16 KSPS on a perch channel, much like a beacon, to facilitate this initial acquisition. The perch channel format includes a frame with sixteen time slots, each having a duration of 0.625 milliseconds. Each time slot includes four common pilot symbols, four transport channel data symbols and two synchronization code symbols. These synchronization code symbols include the FSC and SSC symbols transmitted in parallel. These synchronization code symbols are not modulated by the cell-specific long code, so a mobile receiver can detect the FSC and SSC transmitted by an unknown base station. Proper identification of the FSC and SSC by the mobile receiver, therefore, limits the final search to one of sixteen scrambling codes that specifically identify a base station within the cell to a mobile unit.
Referring to FIG. 2, there is a match filter circuit of the prior art for detecting the FSC and SSC generated by the circuit of FIG. 1. The circuit receives the FSC symbol from the transmitter as an input signal IN on lead 200. The signal is periodically sampled in response to a clock signal by serial register 221 at an oversampling rate n. Serial register 221, therefore, has 15*n stages for storing each successive sample of the input signal IN. Serial register 221 has 16 (N) taps 242-246 that produce 16 respective parallel tap signals. A logic circuit including 16 XOR circuits (230, 232, 234) receives the respective tap signals as well as 16 respective PN signals to produce 16 output signals (231, 233, 235). This PN sequence matches the transmitted sequence from circuit 108 and is preferably a Lindner sequence. Adder circuit 248 receives the 16 output signals and adds them to produce a sequence of output signals at terminal 250 corresponding to the oversampling rate n.
A 16-symbol accumulator circuit 290 receives the sequence of output signals on lead 250. The accumulator circuit 290 periodically samples the sequence on lead 250 in serial register 291 in response to the clock signal at the oversampling rate n. Serial register 291, therefore, has 240*n stages for storing each successive sample. Serial register 291 has 16 taps 250-284 that produce 16 respective parallel tap signals. Inverters 285 invert tap signals corresponding to negative elements of the Lindner sequence. Adder circuit 286 receives the 16 output signals and adds them to produce a match signal MAT at output terminal 288 in response to an appropriate FSC or SSC.
Referring now to FIG. 3A, several problems arise with this method of FSC and SSC transmission and detection. During first step or first stage acquisition, the receiver must match the 256-chip FSC on a first perch channel to identify a base station transmission. In the second stage of acquisition, the mobile receiver must match the SSC to determine which of 32 possible groups of 16 synchronization codes (ScC) are being transmitted and complete frame synchronization by determining which of 16 time slots is the first in the frame. Finally, during third stage acquisition, the receiver must determine which of 16 codes in the code group is being transmitted. This detection scheme, therefore, limits the mobile receiver to identification of a maximum of 512 base stations corresponding to the 32 groups of 16 scrambling codes each. With the current proliferation of base stations and mobile receivers, however, this has become an unacceptable limitation. Furthermore, simply increasing the number of codes per group or the number of groups dramatically increases time and complexity of the mobile receiver match circuit. For example, the present detection scheme requires matching 32 possible codes over 16 possible frames or 512 possible combinations. Thus, an increase to 64 groups would introduce 1024 possible combinations to match. Finally, the time and power required to match such an inordinate number of combinations is prohibitive.
Turning now to FIG. 3B, other designs of the prior art have tried to resolve this problem by adding a separate step for frame synchronization prior to synchronization code group identification. These modifications to the synchronization scheme also envision an alternative embodiment wherein synchronization code group identification precedes the frame synchronization step (FIG. 3C). This modified synchronization scheme (FIG. 3B) adds a third synchronization code (TSC) dedicated to frame synchronization (FIG. 4). This dedicated code enables the receiver to complete frame synchronization prior to synchronization code group identification. The TSC is transmitted on a third perch channel at the same symbol time as the FSC and SSC. The long code or original ScC is masked during this symbol time, so that none of the FSC, SSC or TSC are modulated by this long code. The TSC, however, is transmitted only on eight even numbered time slots [0,2,4, . . . ,14] of each frame and utilizes the same eight 256-chip codes per frame for each code group.
Several problems with the modified synchronization scheme of FIG. 3B and FIG. 3C render them less than ideal. First, additional power allocated to the TSC will limit system capacity. Second, a balance of power becomes more complex due to TSC codes only on alternate frames. Finally, although SSC matching is simplified, it remains complex and time consuming.
These problems are resolved by a method of processing data comprising receiving a frame of data having a predetermined number of time slots, wherein each time slot comprises a respective plurality of data symbols. The method further comprises receiving a primary, a secondary and a tertiary synchronization code in each said predetermined number of time slots.
The present invention reduces circuit complexity of FSC, SSC and TSC identification. Identification time, processing power and circuit complexity are further reduced.